Control System of Large Screen LED Monochrome Graphic Display Screen Based on FPGA

At present, the small and medium-sized LED display systems in the market generally use the traditional single chip microcomputer as the main control chip. For the LED large screen display, due to the large amount of data transmission, the scanning speed is required to be fast, while the internal resources of the single chip microcomputer are less and the running speed is slow, which is difficult to meet the system requirements. FPGA is used as the controller. On the one hand, FPGA uses software programming to realize hardware functions, which is fast; On the other hand, it has rich pin resources and strong scalability. Therefore, the control of large screen LED display screen can be realized by using single-chip FPGA and simple peripheral circuit without designing Chinese character library. It has the advantages of high integration, good stability, flexible design and high efficiency.

1. Overall system structure

The LED large screen display system is composed of upper computer (PC), single chip microcomputer system, FPGA controller, row and column driving circuit of LED display screen and other modules, as shown in Figure 1. The upper computer is responsible for the collection and transmission of Chinese characters, characters and other data. The single chip microcomputer system and the upper computer work in the mode of asynchronous serial communication. The graphic dot matrix data to be displayed which has completed format conversion is obtained from the upper computer through the serial port, and stored in EEPROM memory. Then, the display data of the memory is restored to the LED display screen through the FPGA controller. The scanning control circuit adopts programmable logic chip cyclone ep1c6, which is programmed with VHDL language, adopts 1 / 16 scanning mode, and the refresh frequency is above 60 Hz. This paper focuses on 256 & times; FPGA control module of 1024 monochrome graphic display screen.

2. Basic working principle of LED display

For the large screen LED display, the column display data usually adopts the serial transmission mode, and the row adopts the 1 / 16 scanning mode. Figure 2 shows 16 & times; The basic structure of 32 dot matrix screen unit module, and the column drive circuit is cascaded by four 74HC595. Under the action of the shift pulse srclk, the serial data is input bit by bit from the data port ser of 74HC595. When all 32 columns of data in a row are transmitted, the latch signal rCLK is output and the pass signal Y0 is selected, then each column of data in the first row can be displayed as required. The remaining rows are displayed in the same way. When 16 rows of data are scanned once (i.e. one cycle is completed), the scanning of the next cycle starts from the first row. As long as the scanning period is less than 20 ms, the display does not flash.

256&TImes; 1024 large screen display consists of 16 & times; 16 of 32 32 dot matrix screens are cascaded. In order to shorten the signal transmission time from the control system to the screen, the display data is divided into 16 areas, each area is composed of 16 1024 dot matrix, each line of data is 1024 / 8 = 128 bytes, the pixel signal of the display screen is transmitted and shifted from the right side to the left side of the LED display screen, and the data of 16 partitions are stored in the same memory. The display data of one screen is 32 KB. To accurately read the data of 16 partitions, the read address of the memory is composed of 16 bits. Since the data is only 32 KB, it can be set to 0 at most. The other 15 bit addresses are row address (4 bits), column address (7 bits) and partition address (4 bits) from high to low. The decoded signal (Y0 Y15) of the 4-bit partition address is used as the latch pulse of the latch. Within 16 read address generation cycles, the first byte data of the 1st 16th partitions are successively latched to the corresponding latch, and then the 16 byte data is simultaneously latched into 16 8-bit parallel to serial shift register groups at the rising edge of the shift latch signal. In the next 16 read address generation clock cycles, on the one hand, the parallel to serial shift register shifts the 8-bit data to serial output, and the shift clock is the frequency division of the read address generation clock; On the other hand, the second byte data of 16 partitions are sequentially read out and locked into the corresponding latch. After all the first row data of all partitions are sequentially read out according to this law, all serial shift data are output on the rising edge of the data effective pulse signal to drive the LED display. Next, the data of the second row is shifted and output, and the first row remains displayed during this period; After all the second line is moved in, drive the second line display and move in the third line at the same time... Complete the scanning and display of the whole LED large screen in this way of branch scanning of each partition.

3 design of display controller based on FPGA3.1 overall scheme of FPGA control moduleAs shown in Figure 3, the FPGA control module is mainly composed of MCU and FPGA interface, data reading and writing module, read address generator, decoder, row address generator, data latch group, shift register group, pulse generator and other modules.

The read address generator mainly generates the read address signal, which is sent to the MCU interface and data read-write module to read the processed LED display data in the external sram1 or sram2, and send the data to the data latch group for locking according to the partition mode. The latch outputs 16 partition data, realizes parallel serial conversion through the shift register group, obtains the serial data required by the display screen, and sends it to the LED display screen column drive circuit. The pulse generator provides the corresponding synchronous clock for each module, and the line address generator generates the corresponding line signal and sends it to the line driving circuit of the display screen.

3.2 interface between MCU and FPGA and data reading and writing module

The interface between MCU and FPGA and the structure of data reading and writing module are shown in Figure 4. After the single chip microcomputer reads the data from EEPROM and processes it according to the display requirements, it sends the data to the data buffer sram1 or sram2 through the interface and data reading and writing module. In order to improve the data transmission speed and ensure the continuity of display effect, the dual body switching technology is used to complete the data storage process in the system. In other words, the dual SRAM storage structure is adopted, and two sets of completely independent read and write address lines and data lines are switched in turn for reading and writing. When working, FPGA only reads the displayed data from one of the two SRAMs for display at a specific time, and the other SRAM exchanges data with MCU. MCU will write new data and work alternately in turn to realize display modes such as left shift, up shift and double screen. If the displayed content does not change, that is, the data in one SRAM remains unchanged, MCU does not need to write data to another SRAM.

The module is implemented by VHDL finite state machine. The whole control is divided into four states, and the state transition diagram is shown in Figure 5. The working process is as follows: the system starts up and enters the initial state st0, the write enable end e of the single chip microcomputer is low level, the single chip microcomputer reads the data from the EEPROM and writes the data to sram1, and the FPGA reads the data in sram2 at the same time; When the MCU data writes a screen of data, e changes to high level, and when the FPGA reads the data from sram2 and ends the signal read_ End is low level and enters ST1 state.

In ST1 state, if no new data is written, e remains high, and FPGA reads the data of sram1 for static display; Only when the read in control signal e of the single chip microcomputer is low and read_ End is at low level and enters ST2 state. In the ST2 state, the single chip microcomputer writes the data into sram2, and the FPGA reads the data of sram1. After the single chip microcomputer writes the data, e becomes high level, and when the FPGA reads the data on one screen, read_ End is low level and enters ST3 state. In ST3 state, if no new data is written, e is high level, FPGA reads the data in sram2. When the MCU has new data written, e becomes low level, and read after reading the data on one screen of FPGA_ When end is low level, re-enter st0 state. Through this cycle of alternating work to complete data writing and reading, the port program is as follows:

3.3 read address generatorThe read address generator mainly generates the read address signal of the external buffer sram1 (sram2), so that the system can correctly read the corresponding display data from the memory. The highest bit of the address is 0, and the other addresses are 15 bit effective address signals of row address (hang [3.. 0]), column address (lie [6.. 0]) and partition address (Qu [3.. 0]). Read out 16 byte data in sram1 (sram2) within 16 pulse cycles, and some VHDL source programs are as follows:3.4 decoder

The decoder module mainly generates 16 partition signals (low-level effective), controls 16 latches respectively, and locks the display data of 16 partitions in the corresponding latches respectively.3.5 data latch group and shift register group moduleThe data latch group module consists of 16 8-bit latches, which latch the data of 16 partitions. The shift register group module is composed of 16 8-bit shift registers, which converts the 8-bit parallel data in each latch into 16 channels of serial data output at the same time, drives the LED display screen and realizes the parallel serial conversion of data.

The generated component symbols are shown in Figure 6. Among them, data in [7.. 0] is the 8-bit parallel data input of each partition, SCLK is the shift clock, CLR is the zero clearing signal, load is the data latch signal, CS [15.. 0] is the input signal of 16 partition (connected to the output of decoder), data_ Out [15.. 0] is 16 channel serial data output.3.6 pulse generator

The system adopts 1 / 16 scanning mode to divide the data into 16 partitions, and the data in 16 partitions are transmitted at the same time. Assuming that the refresh frequency is 60 Hz (i.e. the period is 16.67 MS), the display time of each line is about 16.67 MS / 16 = 1.04 Ms. If there are 1024 bits in each line, the shift pulse period is 1.04 / 1024 = 1.02 s. That is, the shift frequency above 0.983 MHz can meet the requirements. Since the shift pulse is 2 frequency division of the clock of the data reading module, the clock of the system is at least 1.97 MHz. The system adopts 50 MHz clock source. The timing diagram is shown in Figure 7.

Wherein, rdclk is the FPGA read data clock; SCLK is the shift clock of serial output and the 2-frequency division of rdclk; Load is a data latch signal. A latch signal is generated after reading a byte data in 16 partitions each time. The data is locked in the data latch group, and its clock is 16 frequency division of rdclk.4 simulation test of FPGA control module

A project is established in QuartusII 5.1, and the schematic diagram file is established. The module element symbols generated by the interface between MCU and FPGA and the unit modules such as data reading and writing module, read address generator, decoder, line address generator, data latch, shift register and pulse generator are connected to form the logic diagram of the general control module and simulate its function. The simulation results are shown in Fig. 8. 16 bytes of data are read from the memory and 16 channels of serial data are output through parallel serial conversion. From the waveform analysis, the function is correct, and the signals of each output port meet the timing requirements.

epilogueFPGA is an on-line programmable chip, which can be programmed according to different user requirements, which shortens the development cycle of the system and saves the development cost of hardware. In this paper, FPGA is the main chip, and the control system of large screen LED monochrome graphic display screen is designed completely. With the development of LED display technology, the combination of FPGA and arm or DSP will be widely used in the field of two-color display and color display.